1. Field of the Invention
This invention relates to an adaptive memory redundancy method and apparatus for integrated circuits having an on-chip processor and embedded memory. More particularly, it relates to a method and apparatus to adaptively replace defective memory in a device including an on-chip processor and embedded memory.
2. Background of Related Art
Many integrated circuits today include a processor and large amounts of embedded memory. It is typically difficult to manufacture such devices to have all words of memory operable. Oftentimes, certain bits of memory are defectively manufactured. However, instead of discarding the integrated circuit, memory redundancy techniques have been conventionally implemented which replace portions of the embedded memory containing defective bits so as to make the device acceptable for use. Thus, conventional memory redundancy techniques generally improve manufacturing yield.
In conventional memory redundancy techniques, extra rows, columns or blocks of memory are manufactured along with the required rows and columns of memory. If any one row, column or block of memory contains a defective memory cell, the entire row, column or block is eliminated, typically by laser etching a fuseable link to permanently modify the device circuit. The laser etching is a permanent fix based on the pre-installation test and analysis of the device, usually performed during a wafer test phase of the manufacturing process.
While being a well established method of memory redundancy, the conventional methods suffer from increased costs of manufacture due to the additional equipment, test time and process modifications required to test, locate and replace defective memory cells.
There is a need for a more efficient, cost effective and reliable approach to correct defects in memory circuits. There is also a need to adaptively correct or overcome defects in embedded memory circuits which occur even after device manufacture.